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hdl课程设计报告.doc

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hdl课程设计报告.doc

上传人:2286107238 2022/8/18 文件大小:78 KB

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【关键词】自动售货机 Verilog HDL FPGA Quartus II
ABSTRACT
Verilog HDL is a widely used hardware description language that can be used from the algorithm level, gate-level to the switch-level abstraction of a variety of levels of digital system design. Because of this language is simple, efficient, easy to use, powerful, so many designers gradually accepted widely popular, especially in the ASIC design in the mainstream. Verilog hardware description language to language used in the manner described in soft hardware features, and can plete the circuit emulation mode debugging, making the hardware development cycle and greatly reduce the cost, this article describes the characteristics and application of Verilog HDL, and vending machines, for e*ample , details the process of its implementation, and gives the implementation code and simulation waveforms.
This design is an auto-vending machine based on field programmable logic devices (FPGA) . We use QuartusⅡ to write procedure in verilog HDL which is a language to describe hardware. The procedure will realize the function of auto-vending machine.
This design is mainly about procedure. For the hardware, we use e*perimental bo*. We allocate all variable quantities in the procedure to the feet in e*perimental bo*. We use eight switch respectively represent modity prices and throw money price and confirm payment change operation. When choosing good modities and coin, digital pipe display selected modity prices and money price. When pressing confirm payment switch, digital pipe display should find how much money, buzzer sounded, corresponding modity LED lights. If throw money shortage selected modity prices, corresponding warning money shortage of LED lights.
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