组合逻辑电路实验报告.docx

文档介绍：成绩
数字电子技术实验报告
实验名称:组合逻辑电路
班级姓名学号
实验日期年月日交报告日期年月日
组合逻辑电路
一、设计要求
,比如。
,并在开发板上验证。
,实现将8个SW输入的两位十六进制数对应的8421BCD码,显示在数码管上。
二、实验内容
任务1:实现逻辑功能
(1)HDL源文件——
module ge(
input a,
input b,
input c,
input d,
output[0:0]z
);
assign z[0]=~((a&b)|(c&d));
endmodule
(2)约束文件——
NET"a"LOC=P11; //SW0
NET"b"LOC=L3; //SW1
NET"c"LOC=K3; //SW2
NET"d"LOC=B4; //SW3
NET"z[0]"LOC=M5; //LD0
(3)仿真文件——
initial begin
a = 0;b = 0;c = 0;d = 0;
// Wait 100 ns for global reset to finish
#100
a<=0;b<=0;c<=0;d<=1;
#200
a<=0;b<=0;c<=0;d<=1;
#200
a<=0;b<=0;c<=1;d<=0;
#200
a<=0;b<=0;c<=1;d<=1;
#200
a<=0;b<=1;c<=0;d<=0;
#200
a<=0;b<=1;c<=0;d<=1;
#200
a<=0;b<=1;c<=1;d<=0;
#200
a<=0;b<=1;c<=1;d<=1;
#200
a<=1;b<=0;c<=0;d<=0;
#200
a<=1;b<=0;c<=0;d<=1;
#200
a<=1;b<=0;c<=1;d<=0;
#200
a<=1;b<=0;c<=1;d<=1;
#200
a<=1;b<=1;c<=0;d<=0;
#200
a<=1;b<=1;c<=0;d<=1;
#200
a<=1;b<=1;c<=1;d<=0;
#200
a<=1;b<=1;c<=1;d<=1;
end
(4)仿真波形
分析:由仿真波形可见,所以程序实现了。
(5)开发板验证
a
b
c
d
z
SW0
SW1
SW2
SW3
LD0
0
0
0
0
亮
1
1
0
0
不亮
1
0
0
1
亮
可见实现了
任务2:4选1多路选择器的设计与验证
(1)HDL源文件——
module ge1(
input wire a0,
input wire a1,
input wire a2,
input wire a3,
input wire s1,
input wire s0,
output wire y
);
assign y=(a0&(~s1)&(~s0))|(a1&(~s1)&s0)|(a2&s1&(~s0))|(a3&s0&s1);
endmodule
(2)约束文件——
NET"a0"=P11; //SW0
NET"a1"=L3; //SW1
NET"a2"=K3; //SW2
NET"a3"=B4; //SW3
NET"s1"=G3; //SW4
NET"s0"=F3; //SW5
(3)仿真文件——
initial begin
// Initialize Inputs
a0=0;a1=0;a2=0;a3=0;s1=0;s0=0;
// Wait 100 ns for global reset to finish
#100
a0<=1;a1<=0;a2<=0;a3<=0;s1<=0;s0<=0;
#100
a0<=0;a1<=1;a2<=0;a3<=0;s1<=0;s0<=0;
#100
a0<=0;a1<=1;a2<=0;a3<=0;s1<=0;s0<=1;
#100
a0<=0;a1<=0;a2<=1;a3<=0;s1<=0;s0<=1;
#100
a0<=0;a1<=0;a2<=1;a3<=0;s1<=1;s0<=0;
#100
a0<=0;a1<=0;a2<=0;a3<=1;s1<=1;s0<=0;
#100
a0<=0;a1<=0;a2<=0;