文档介绍：One-Level Storage System
Kilburn, Edwards, Lanigan, Sumner (1961)
Superset of: Dynamic Storage Allocation in the puter, Including
an Automatic Use of Backing Store, Fotheringham (1961).
What kind of paper?
•New idea.
•Motivation.
•Explanation.
•Algorithms.
Atlas Architecture
48-bit word
24-bit half words
10-bit 7 bit 7 bit 24-bit store address
opcode
index registers
0: main memory character offset
1: executive store top bit ids half-word op
•87-bit FP accumulator.
•128 24-bit index registers (90 available for general use).
•Executive store includes ROM for Supervisor.
Computer Science 261
Copyright 2005 Page 1 of 3
Memory Arrangement
•512-byte blocks/pages.
•One Page Address Register per in-memory (core) page.
•PAR contains the address of the page currently resident in memory.
•Priority scheme of handling tape and drum.
•First drum (4 usec).
•Next tape (11 usec).
•Rest of time goes to core store.
•Memory is banked into 4 stacks.
Motivation for single-level store
•Too expensive to make entire memory core store.
•Too slow to make entire memory drum.
•Desire: performance of core at cost of drum.
Implementation of single-level store
•Fully associative lookup on every address (like a TLB; how large is
their lookup? 32 entries; why wouldn’t that work today).
•If address found in a PAR, then the data is returne