文档介绍：Digital System Test and Testable Design
Zainalabedin Navabi
Digital System Test
and Testable Design
Using HDL Models and Architectures
Zainalabedin Navabi
Worcester Polytechnic Institute
Department of Electrical & Computer
Engineering
Worcester, MA
USA
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ISBN 978-1-4419-7547-8 e-ISBN 978-1-4419-7548-5
DOI -1-4419-7548-5
Springer New York Dordrecht Heidelberg London
Springer Science+Business Media, LLC 2011
All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the
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Printed on acid-free paper
Springer is part of Springer Science+Business Media ()
This book is dedicated to my wife, Irma, and sons
Aarash and Arvand.
Preface
This is a book on test and testability of digital circuits in which test is spoken in the language of
design. In this book, the concepts of testing and testability are treated together with digital design
practices and methodologies. We show how testing digital circuits designing testable circuits can
take advantage of some of the well-established RT-level design and verification methodologies and
tools. The book uses Verilog models and testbenches for implementing and explaining fault simula-
tion and test generation algorithms. In the testability part, it describes various scan and BIST meth-
ods in Verilog and