文档介绍：摘要
以外商委托的科研项目“深亚微米电源管理类集成电路及各种数模混合集成电路的关键技术理论研究与设计”为背景,作者承担了高效电流模同步降压型DC/DC集成电路设计与实现工作。目前作者所设计芯片已经通过Cadence、Hspice等EDA软件前、后仿真验证、CMOS的版图设计,正于Hynix投片。
论文以开关型电压转换器为着眼点,在深入、系统地分析和研究了电流模开关型电压转换器的基础上,成功地设计与实现了一款高效电流模降压型DC/DC。该芯片采用同步整流、双工作模式、低漏电压等技术使得最高效率可达96%。为了消除大占空比工作时的亚谐波振荡效应,作者对斜率补偿技术进行了深入的分析研究,并在此基础上设计了斜率补偿电路。其中,大胆设计了一款可根据斜率补偿信号幅度进行阈值自调节的箝位电路,从而大大消除了斜率补偿对电流限制的影响,保证了芯片在高占空比条件下的带载能力。为了保证该DC/DC电压环路稳定,文章对芯片中工作于开关态的电路进行建模,并得到波特图,从而恰到好处地实现了电压环的频率补偿。结合市场需求,为了缩短芯片测试周期,提高产品利润,文章采用管脚复用技术,完成了可测性设计。
关键词:电流模 Buck型DC/DC 斜率补偿稳定性可测性
ABSTRACT
A high efficiency current mode synchronous buck regulator IC is designed on the basis of the project “Theoretical research and design of key techniques for deep-submicron power management IC and mixed IC”. The whole simulation has pleted by using the EDA softwares, such as Cadence, Hspice, and the layout design is also finished. At present, the chip is being taped out in Hynix.
Beginning from the switching mode regulator, a high efficiency current mode synchronous buck DC/DC is designed after an in-depth systemic study on the current-mode switching regulator. By adopting the technologies of synchronous rectification, double operation mode and low dropout operation, the efficiency of this design is up to 96%. In order to prevent the sub-harmonic oscillation at high duty cycles, pensation is used. What is special is that the design provides a clamp circuit that can adjust its thresholds with respect to the magnitude of the pensation signal so that a substantially constant maximum current limit of the regulator may be remained at greater duty cycles. A macro model is also created to obtain the bode plots for appropriate pensation. Finally, the circuits for testability are designed to shorten the test time and get more profit margins.
Keyword: current-mode Buck regulator pensation stability
testability
目录
第一章绪论 1
§ 1
§ 2
第二章 XD2607系统构建 8
§ 8
§ 10
§ 11
§ 13
§ 主要电特