文档介绍：EB1 EB2 Tester_2 软件设计
第一部分原理图
DeltaSigmaClk
U1 U_SineWaveGenerator U2 U_DeltaSigma8
I[15..0] U3 OA[7..0]
NoteN[7..0] NOTEN[7..0] / N Clock DOUT[7..0] A[7..0] P[15..0] CLK SoundOut AudioOut
CNTL[15..0]
DIVIDERRATIO[15..0] B[7..0]
LOAD OB[7..0]
GND DataIn[7..0]
CDIVN_16 MULTU8B J16B_8B2
U4
Invalid
Reset
Reset
OR2S
Vol[7..0]
--Entity name
--Created ()
--Created by .
--Modified (date, by whom)
--Description
--Tristate IO Buffer
Library Ieee;
use ;
entity addTrans is
port (
sel : in std_logic;
inp : in std_logic_vector(15 downto 0);
outp : out std_logic_vector(15 downto 0);
io : inout std_logic_vector(15 downto 0)
);
end entity;
architecture rtl of addTrans is
begin
outp <= io when sel = '0' else (others=>'Z');
io <= inp when sel = '1' else (others=>'Z');
end architecture;
{..............................................................................}
{ Summary }
{ Converts a monochrome image as a PCB Logo into a series of thin }
{ PCB tracks that can be placed on a PCB document as a logo. }
{ }
{ Copyright (c) 2008 by PurPer Limited }
{ }
{ Version }
{ }
{ C