文档介绍：IP Core Design
Outline
Intellectual Property (IP) Core: basics
IP Core classification
IP Core standardization
Standard buses/interfaces for IP Cores
IP Cores in the market
Example with FIR piler
IP Core: basics
Intellectual Property (IP) core:
“Macro” structures with specific industrial-standard function that can be
flexibly be adapted and reused in SoC designs.
From “sea of cells” to “sea of hard macros”
* Figures extracted from [2].
IP Core classification
Criteria Classification
Hard core
Soft core
Structure
Pre-anization.
Behavioural source code, technology independent.
Modelling
Modeled as a ponent.
Synthesizable with several technologies.
Flexibility
Cannot be modified by the designer.
Can be modified by the designer.
Timing closure
Timing ensured.
Timing not guaranteed.
IP protection
Strong. Usually corresponds to a layout.
Weak. Source code.
Example
FPGA Bitstream. GDSII file for IC layout.
VHDL, Verilog.
* Partially extracted from [1].
IP Classification: hard cores and soft cores
IP Core standardization
VSI Alliance (VSIA)
Open, anization
Specify standards for IP and reuse in SoC designs
Quality IP (QIP) Metric
Open Measure of Reuse Excellence (OpenMORE) assessment program
Donated by Mentor Graphics / Synopsys to VSIA
Evaluate the reusability level of hard/soft IP cores
Open Core Protocol International Partnership (OCP-IP)
Non-anization that promotes the Open Core Protocol (OCP)
Specify standards for IP cores in SoC designs
Payment to have access to specifications
Structure for Packaging, Integrating and Re-using IP within Tool-flows (Spirit) Consortium
Create standards for IP interoperability:
Standard for describing IP cores
Standard for creating an IP tool integration API
IP Core standardization
Technology-pany-based certifications:
Altera SOPC Builder ready
AMPP Approved Stamp
Xilinx AllianceCore qualification
Lattice ISPLeverCore Approved
Standard bus/interface for IP