文档介绍：EDA设计基础实验课程论文
项目名称基于FPGA IP核的FFT设计与实现
学院通信与电子工程学院
专业班级通信104
学生姓名姜允鑫
指导教师董亮

2013 年 6 月 12 日
摘要
快速傅立叶变换(FFT)作为时域和频域转换的基本运算,是数字谱分析的必要前提。传统的FFT使用软件或DSP实现,高速处理时实时性较难满足。FPGA是直接由硬件实现的,其内部结构规则简单,通常可以容纳很多相同的运算单元,因此FPGA在作指定运算时,速度会远远高于通用的DSP芯片。FFT运算结构相对比较简单和固定,适于用FPGA进行硬件实现,并且能兼顾速度及灵活性。本文介绍了一种通用的可以在FPGA上实现32点FFT变换的方法。设计复数乘法器为核心设计了FFT算法中的基-2蝶形运算单元,溢出控制单元和地址与逻辑控制模块等其它模块,并以这些模块和FPGA内部的双口RAM为基础组成了基-2FFT算法模块。整个模块采用基-2时域抽取,顺序输入,逆序输出的方法;利用Modelsim完成了FFT模块的前后仿真;利用Matlab编写了用于比较仿真结果和Matlab中FFT函数产生的结果的程序,从而验证了仿真结果的正确性。实验果表明,设计完成的系统能够在保证运算精度和实现复杂度的同时,切实可行地完成设计的总体要求。
关键词: 现场可编程门阵列; 快速傅立叶变换; IP核; 基2; 时域抽取
Abstract
Fast Fourier Transform (FFT) as the time domain and frequency domain transformation of the basic operations is a necessary prerequisite for digital spectrum analysis. The traditional FFT implementation using software or DSP, high-speed real-time processing is more difficult to meet. Directly from the FPGA hardware, and its internal structure rules are simple, usually to modate many of the same operation unit, so as specified in puting, the speed will be much higher than the general DSP chips. putation structure is relatively simple and fixed, suitable for hardware implementation using FPGA, and can take into account the speed and flexibility. This paper presents a generic FPGA can be implemented on 32 points in the FFT transform method. Design plex multiplier for the core design of the FFT algorithm based -2 butterfly unit, overflow control unit and address logic control module and other modules, and within these modules and FPGA-based dual-port RAM formed the base - 2FFT algorithm module. When the module is the base -2 domain extraction, the order of input, output reverse method; use Modelsim before and after pletion of the FFT module simulation; prepared using Matlab and Matlab simulation results for parison function in the FFT result of the procedures to verify the correctness of the simulation results. Experimental results show that the design pleted