文档介绍：毕业设计
学生姓名: 洪雷学号: 09xxxxxxxx
专业: 电子科学与技术
题目: 基于FPGA的DDR2存储器控制器设计
指导教师: 安国臣(讲师)
评阅教师: 武瑞红(副教授)
2013年6月
毕业设计中文摘要
随着消费电类电子产品以及便携式通讯产品向多功能、高性能和低功耗方向的飞快发展,而随之带来的是对大量的数据处理,而产品的系统对其主要的存储设备的要求也越来越高。目前,DDR2凭着其及其高的数据传输速率和低廉的成本则越来越多的被用到一些高档类的消费类电子和便携式产品中。对DDR2 SDRAM的控制器处理的设计变得也就非常有必要。
使用FPGA技术设计数字电路,不仅可以简化设计过程,而且还可以减低整个系统的体积和成本,增加系统的可靠性。本次设计则使用Altear公司的Cyclone V代器件,经行开发的最小系统。
本次设计使用的是Mircon公司的MT47系列的芯片,借助Altera公司提供的IP核所自动生成PHY接口。由于DDR2的读写驱动的要求,多次设计了电压的要求。
本文对DDR2 SDRAM基本结构和原理进行了简单的介绍。并且阐述基于FIFO和PHY接口的DDR2设计方法。
关键词 DDR2 FPGA 存储器控制器 FIFO
毕业设计外文摘要
Title DDR2 Memory Controller Design based on FPGA
Abstract
As consumer electric class electronic products and munication products to multi-functional, high performance and low power consumption direction of rapid development, and then brings about a lot of data processing, the product of the system to the main storage device requirements more and more higher. At present, the DDR2 with its and high data transfer rate and low cost are more and more used in some high-end consumer electronics and portable products. Processing of DDR2 SDRAM controller design es and is very necessary.
Digital circuit design using FPGA technology, not only can simplify the design process, but also can reduce the size and cost of the whole system, increase the reliability of the system. This design USES pany Cyclone V generation device, the smallest system development.
This design USES the Mircon MT47 series chips, and IP core provided by Altera corporation how can automatically generate the PHY interface. Driven requirements due to DDR2, speaking, reading and writing, and design the voltage requirements for many times.
in this paper, the basic structure and principle of DDR2 SDRAM has carried on the simple introduction. And in this paper, the DDR2 design method based on FIFO and PHY interface
Key Words DDR2 FPGA memory controlle FIFO
目录
1 绪论 1
2 动态随机存储器 3
同步动态随机存储器原理与结构 3
双倍动态随机存储器原理与特点 3
DDR2随机存储器的简介 4
3 可编程逻辑器件原理