文档介绍：硕士学位论文
摘要
集成电路系统复杂度和工艺复杂度的增加,特别是片上系统(SOC)的出现,
使得集成电路测试面临越来越多的挑战。在数字电路测试过程中,测试功耗要远远
高于正常模式下的功耗。产生这一现象一方面是由于测试向量之间的相关度很小;
另一方面是因为测试时需要电路中尽可能多的结点发生跳变。由于被测电路可能在
测试过程中因功耗过大而被损坏,因此降低测试功耗已成为测试开发的一个重要目
标,测试功耗已成为影响数字电路可测试性设计的重要问题。
本文首先对数字电路测试技术的方法进行了概述,分析了电路测试功耗产生的
原因,并列举了现有可测试性设计中几种降低功耗的方法。
接着,对内建自测试(BIST)方法中测试向量生成过程进行了分析,指出采用
LFSR 做测试产生时所遇到的问题。针对这一问题,在统计分析测试集中有效测试
向量分布规律的基础上,提出了基于片段间转移的低功耗 BIST 策略。该策略通过
故障模拟软件去除了测试集中对故障覆盖率没有贡献的无效测试向量,并将剩余的
有效测试片段依据测试功耗最低的原则排序后,依次送入被测电路。
在该策略的基础上,实现了基于片段间转移的低功耗 BIST 结构,并结合各组
成部分的功能,详细地介绍了该 BIST 结构在两个阶段的运行过程:有效片断内部
生成过程和片断间转移过程。仿真结果显示,采用该低功耗 BIST 结构避免了大量
无效测试向量的运行,降低了测试功耗,减少了测试时间。
最后,介绍了一种被测电路自反馈测试的基本思想。针对自反馈测试中存在部
分输入不能被反馈这一问题,提出了基于异或的反馈输入生成算法,并通过添加移
位寄存器,增加了寻找成功率,降低了硬件代价。仿真数据表明,该算法可以作为
自反馈测试的有效补充。
关键词:低功耗测试;内建自测试;测试片段;自反馈测试;向量距离
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基于片断间转移的低功耗测试结构研究与实现
Abstract
Due to the growth of plexity of digital integrated circuit, especially the
appearance of system-on-a-chip, testing faces more and more challenge. During the
process of IC testing, the power dissipation is much higher than that of normal operation.
There are two reasons for this phenomenon. One is the correlations between vectors are
small. The other is testing needs switching nodes as many as possible. The power
dissipation could damage the IC during the process of testing. Therefore, reducing power
consumption has e an important target in testing technology and power dissipation
has profound influence on design for testability.
In this paper, firstly the function and basic principle of digital circuit testing
technology is introduced, the cause of circuit test power is analyzed and several methods
to reduce test power in present design for testability is enumerated.
Secondly, based on the analysis of the process of test pattern generation during BIST
process, the problem caused by LFSR as test generator is pointed out. In order to solve
the problem, a low-power BIST strategy based on segment transfo