文档介绍：Advanced PCB Design and Layout for EMC Part 8 - A number
of miscellaneous final issues
By Eur Ing Keith Armstrong MIEE MIEEE, Cherry Clough Consultants
This is the last in a series of eight articles on good-practice design techniques for
patibility (EMC) for printed circuit board (PCB) design and layout. This
series is intended for the designers of any electronic circuits that are to be constructed on PCBs,
and of course for the PCB designers themselves. All applications areas are covered, from
household appliances; commercial, medical and industrial equipment; through automotive, rail
and marine to aerospace and military.
These PCB techniques are helpful when it is desired to.
Save cost by reducing (or eliminating) enclosure-level shielding
Reduce time-to-market pliance costs by reducing the number of design iterations
Improve the range of co-located wireless ms (GSM, DECT, Bluetooth, IEEE
, etc.)
Use very high-speed devices, or high power digital signal processing (DSP)
Use the latest IC technologies (130nm or 90nm chip processes, ’chip scale’ packages,
etc.)
The topics to be covered in this series are:
1. Saving time and cost overall
2. Segregation and interface suppression
3. PCB-chassis bonding
4. Reference planes for 0V and power
5. Decoupling, including buried capacitance technology
6. Transmission lines
7. Routing and layer stacking, including microvia technology
8. A number of miscellaneous final issues
This is the final part of this series, and I hope you have enjoyed reading it, or at least
found some things in it that were interesting or useful.
A previous series by the same author in the pliance Journal in 1999 "Design
Techniques for EMC" [1] included a section on PCB design and layout ("Part 5 - PCB
Design and Layout", October 1999, pages 5 - 17), but only set out to cover the most basic
PCB techniques for EMC - the ones that all PCBs should follow no matter how simple
their circuits