文档介绍：Design and PCB Layout Considerations
for Dynamic Memories
interfaced to the Z80 CPU
by
Tim Olmstead
10-01-96
Interfacing dynamic memories to microprocessors can be a demanding process. Getting DRAMs
to work in your prototype board can be even tougher. If you can afford to pay for a multi-layer
PCB for your prototype you will probably not have many problems. This paper is not for you.
This paper is for the rest of us.
I will break down the subject of DRAM interfacing into two categories; timing considerations
for design, and layout considerations. Since information without application is only half the
battle, this information will then be applied to the Z80 microprocessor.
TIMING CONSIDERATIONS
In this day, given the availability of SIMM modules it would be tempting to concentrate only on
these parts. But, to do so would bypass a large supply of surplus parts that might be very
attractive to homebuilders. We will then examine several different types of DRAM chips. The
main distinction between these parts is whether they have bi-directional I/O pins, or separate IN
and OUT pins. Another distinction will affect refresh. Will the device support CAS-before-RAS
refresh, or not?
Let's begin at the beginning. Let's have a look at some basic DRAM timing, and how we might
implement it.
RAS*
CAS*
ROW ADDRESS COL ADDR DON'T CARE
Figure 1. Basic DRAM read timing.
1
The basic timing diagram for a read cycle is shown in figure 1 above. Two control signals are
used to sequence the address into the device; RAS, or Row Address Strobe, and CAS, or
Column Address Strobe.
The address is multiplexed into dynamic memories to conserve package pins. To access a 64K
DRAM device, you would need sixteen address lines. Without multiplexing, this would require
sixteen pins on the package. That's a lot of pins. By today's standards, a 64K DRAM is very
small. To support a modern 16MB part you would need 24 pins. This would lead to some very
large devi