文档介绍：Hardware Acceleration of EDA Algorithms
Kanupriya Gulati · Sunil P. Khatri
Hardware Acceleration
of EDA Algorithms
Custom ICs, FPGAs and GPUs
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Kanupriya Gulati Sunil P. Khatri
109 Branchwood Trl Department of Electrical & Computer
Coppell TX 75019 Engineering
USA Texas A & M University
******@ College Station TX
77843-3128
214 Zachry Engineering Center
USA
******@
ISBN 978-1-4419-0943-5 e-ISBN 978-1-4419-0944-2
DOI -1-4419-0944-2
Springer New York Dordrecht Heidelberg London
Library of Congress Control Number: 2010920238
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To our parents and our teachers
Foreword
Single-threaded software applications have ceased to see significant gains in per-
formance on a general-purpose CPU, even with further scaling in very large scale
integration (VLSI) technology. This is a significant problem for electronic design
automation (EDA) applications, since the plexity of VLSI integrated
circuits (ICs) is continuously growing. In this research monograph, we evaluate
custom ICs, field-programmable gate arrays (FPGAs), and graphics processors as
platforms for accelerating E