文档介绍：华中科技大学
硕士学位论文
高性能电荷泵锁相环分析与设计
姓名:陶亮
申请学位级别:硕士
专业:半导体芯片系统设计与工艺
指导教师:张道礼
20070528
摘要
高性能频率合成器是现代先进电子设备关键部件之一,对系统性能有着重要影响。
随着通信、雷达、测量等技术的发展,对频率源的稳定度、频率纯度和频率范围提出
了越来越高的要求。其中,电荷泵锁相环因其具有易于集成、锁定速度快、锁定范围
宽等优点,如今已成为广泛应用的一种结构。
本课题是与弥亚微电子(上海)有限公司横向合作项目,公司一款芯片需外接两个
晶振,频率分别为: 和 ,作者的工作为通过锁相环频率合成技
术用已有的频率为晶振来实现时钟供内部电路使用,从而降
低芯片外接电路的成本。
采用自顶向下的设计方法,论文详细介绍了从系统级到电路级设计的整个项目开
发过程。在系统级设计上着重分析了电荷泵锁相环的工作原理,制定电荷泵锁相环各
个子模块设计要求,然后利用 simulink 工具建立系统行为级模型,验证并优化系统设
计参数。在电路级设计过程中给出了电荷泵锁相环各子模块电路(鉴频/鉴相器,电荷
泵电路,压控振荡器,分频器)的详细设计过程,在电路设计过程中着重考虑低功耗
问题,采用了如 m 序列码产生器,源耦合逻辑构成的二分频等电路结构来降低整体电
路的功耗。经模拟仿真验证各个子模块电路均满足设计要求。

关键词: 频率合成器; 电荷泵锁相环; 压控振荡器; m 序列码产生器
I
Abstract
High-performance frequency synthesizer is one of the ponents in the modern
sophisticated electronic equipment, it has an important impact on the performance of
system. With the development munications, radar and measurement technology, the
demands to the stability, the purity and the lock range of frequency source are stricter and
stricter. Among PLLs, the charge-pump PLL(CPPLL) having the advantages of easy
integration, high lock speed, wide lock range, has e a widely used structure
nowadays.
The issue is a lateral cooperation project with Miartech (Shanghai) Co., Ltd., one chip
of pany needs two external crystal oscillators, The frequency is respectively:
and . Author's work is to achieve clock for internal
circuits with the crystal oscillator through PLL frequency synthesizer
technology, thereby reducing external circuit chip cost.
According to top down design method, the paper detailedly introduces the entire
project development process from the system-level to the circuit-level design. In the
system-level design, the analysis focuses on the working principle of the CPPLL, establish
sub-module design requirements of CPPLL and then establish systematic behavioral model
to validate and optimi