文档介绍：moduletb_test;//InputsregCLK_IN1;regRESET;//OutputswireCLK_OUT1;wireLOCKED;//InstantiatetheUnitUnderTest(UUT)s6_clockuut(.CLK_IN1(CLK_IN1),.CLK_OUT1(CLK_OUT1),.RESET(RESET),.LOCKED(LOCKED));initialbegin//InitializeInputs//RESET=0;//lobalresettofinish//#100;CLK_IN1=0;    //AddstimulushereRESET=1;#60RESET=0;foreverbegin#20CLK_IN1=!CLK_IN1;endendendmodule`timescale1ps/1ps(//Clockinportsinput    CLK_IN1,//Clockoutportsoutput    CLK_OUT1,//Statusandcontrolsignalsinput    RESET,output    LOCKED);//Inputbuffering//------------------------------------IBUFGclkin1_buf(.O(clkin1),.I(CLK_IN1));//Clockingprimitive//------------------------------------//InstantiationoftheDCMprimitive//  *Unusedinputsaretiedoff//  *Unusedoutputsarelabeledunusedwire    psdone_unused;wire    locked_int;wire[7:0] status_int;wireclkfb;wireclk2x;DCM_SP#(.CLKDV_DIVIDE     (),.CLKFX_DIVIDE     (1),.CLKFX_MULTIPLY    (4),.CLKIN_DIVIDE_BY_2  ("FALSE"),.CLKIN_PERIOD     (),.CLKOUT_PHASE_SHIFT  ("NONE"),.CLK_FEEDBACK     ("2X"),.DESKEW_ADJUST    ("SYSTEM_SYNCHRONOUS"),.PHASE_SHIFT     (0),.STARTUP_WAIT     ("FALSE"))dcm_sp_inst//Inputclock(.CLKIN        (clkin1),.CLKFB        (clkfb),//         (),.CLK90        (),.CLK180