文档介绍：DESIGNINGCMOSCIRCUITS
FORLOWPOWER
European Low-Power Initiative for
Electronic System Design
Editedby:
DIMITRIOSSOUDRIS
DemocritusUniversityofThrace,Xanthi,Greece
CHRISTIAN PIGUET
CSEM,Neuchatel,Switzerland
COSTAS GOUTIS
UniversityofPatras,Patras,Greece
Series Editors:
RENE VAN LEUKEN
ALEXANDER DE GRAAF
REINDER NOUTA
TU Delft / DIMES,herlands
Kluwer Academic Publishers
Boston/Dordrecht/London
Chapter 5
CIRCUIT TECHNIQUES FOR
REDUCING POWER CONSUMPTION
IN ADDERS AND MULTIPLIERS
Labros Bisdounis
., Athens, Greece
******@.gr
Dimitrios Gouvetas
Odysseas Koufopavlou
University of Patras, Rio, Greece
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Abstract An important issue in the design of VLSI Circuits is the choice of the basic circuit
approach and topology for implementing various logic and arithmetic functions
such as adders and multipliers. In this chapter, several static and dynamic CMOS
circuit design styles are evaluated in terms of area, propagation delay and power
dissipation. The different design styles pared by performing detailed
transistor-level simulations on a benchmark circuit (ripple carry adder) using
HSPICE, and analyzing the results in a statistical way. After parison
between the different design styles, a number of well known types of adders
(ripple carry, carry skip, carry lookahead, carry select etc.) pared in terms
of propagation delay, number of gates and logic transition’s average number.
Furthermore, power measurements parisons for a number of well-known
multipliers are provided. Based on the results of the provided analysis, some of
the tradeoffs that are possible during the design phase in order to improve the
circuit power-delay product are identified.
Keywords: circuit design techniques, circuit macroblocks, adders, circuit styles, multipliers
71
D. Soudris et al. (eds.), Designing CMOS Circuits for Low Power, 71-96.
2002 Kluwer Ac