文档介绍：--------------------------校验:_____________-----------------------日期:_____________时序分析教程时序分析术语时序分析的基本模型时序分析是FPGA的重中之重。开始之前请记住时序分析的基本模型Tco为经过寄存器R1的传输延时Tdelay为经过组合逻辑的传输延时Tsetup为R2本身的建立时间;Tpd(clockslew)为时钟到R1和R2的偏差Launchedge和LatchedgeLaunchedge和Latchedge分别是时序分析的起点和终点。需要指出的是Latchedge时间=Launchedge时间+期望系统周期时间DataArrivalTime和DataRequiredTime这两项时间是TimeQuest时序分析的基础,所有的建立时间余量和保持时间余量都是根据这两项时间来决定的。DataArrivalTime=LaunchEdge+SourceClockDelay+tCO+Register-to-RegisterDelayDataRequiredTime=LatchEdge+DestinationClockDelay–tSU需要注意的是DataArrivalTime和DataRequiredTime在分析不同的时序节点时,计算的公式有所差别。建立时间余量ClockSetupSlack建立关系是指寄存器R1发送的数据在下一次更新(更换)之前,寄存器R2可用最短时间去锁存数据建立时间余量是指从Launchedge经过一些列延迟数据输出稳定后到Latchedge的长度。ClockSetupSlack=DataRequiredTime-DataArrivalTimeInternalRegister-to-RegisterpathsDataArrivalTime=LaunchEdge+workDelaytoSourceRegister+tCO+Register-to-RegisterDelayDataRequiredTime=LatchEdge+workDelaytoDestinationRegister–tSU–SetupUncertaintyInputPorttoInternalRegisterDataArrivalTime=LaunchEdge+workDelay+InputMaximumDelay+Port-to-RegisterDelayDataRequiredTime=LatchEdge+workDelaytoDestinationRegister–tSU–SetupUncertaintyInternalRegistertoOutputPortDataArrivalTime=LaunchEdge+workDelayToSourceRegister+tCO+Register-to-PortDelayDataRequiredTime=LatchEdge+workDelaytoOutputPort–OutputMaximumDelaytCO指寄存器R1的自身特性tSU指寄存器R2的自身特性如上图所示:DataArrivalTime =启动沿时间+Tclk1+Tco+Tdata=4nsDataRequiredTime =锁存沿时间+Tclk2-Tsu 所以:SetupSlack =DataRequiredTime-DataArrivalTime保持时间余量ClockHoldSlack保持时间余量是在两个节点(寄存器)之间,在分析保持关系的过程中“到底有多少剩时间可以提供给寄存器用来确保已存数据的稳定”。ClockHoldSlack=DataArrivalTime-DataRequiredTime由于保持时间余量是指当前Latchedge和下一个Launchedge的距离。所以上面公式可以写成:ClockHoldSlack=DataArrivalTime+数据周期时间-DataRequiredTimeInternalRegister-to-RegisterpathsDataArrivalTime=LaunchEdge+workDelaytoSourceRegister+tCO+Register-to-RegisterDelayDataRequiredTime=LatchEdge+workDelaytoDestinationRegister+tH+HoldUncertaintyInputPorttoInternalRegisterDataArrivalTime=LaunchEdge+workDelay+InputMaximumDelay+Port-to-RegisterDelayDataRequiredTime=LatchEdge+workDelay