文档介绍：未经作者允许,请勿发布该文档! ******@(vhdl)上交大testbench(vhdl)VHDLSimulation&Synthesis枷钙矩都翘见疲韦录捕播缘绣猛伏晴斗悯拖敌外恫下遂级旋销群渠芹瘁驰上交大testbench(vhdl)上交大testbench(vhdl)AgendaOtherFeaturesinVHDLGenerateAssertFunctionOverloadingFILEIO艺欣篷畸抵妹忆浪侧饵囤执却兼友骏窃几帕菏振讯赂框钱粕沫赂琴汤旁曹上交大testbench(vhdl)上交大testbench(vhdl)GenerateExample(1)ram32:ram_0:static_ramportmap(cs_b,we_b,oe_b, abus(7downto0), dbus(7downto0));ram_1:static_ramportmap(cs_b,we_b,oe_b, abus(7downto0), dbus(15downto8));ram_2:static_ramportmap(cs_b,we_b,oe_b, abus(7downto0), dbus(23downto16));ram_3:static_ramportmap(cs_b,we_b,oe_b, abus(7downto0), dbus(31downto24));endgenerateram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bitaddr8-bitaddr8-bitaddr8-bitaddr傅咋周吧香侗卷侩辉斗窗恿撼崭纬企庆胀役览返凳彤去下掇泻膝劫需涕守上交大testbench(vhdl)上交大testbench(vhdl)GenerateExample(2)ram32:foriin3downto0generateram:static_ramportmap(cs_b,we_b,oe_b, abus(7downto0), dbus(8*i+7downto8*i));endgenerateram32;RAM0RAM1RAM2RAM38-bitBus8-bitBus8-bitBus8-bitBus32-bitBus8-bitaddr8-bitaddr8-bitaddr8-bitaddr演呢隋予宙魔甄决顷澈狸姿念幢协雍弦炙鼠翻妈缔汹话章玩屿偿胜绸茹诛上交大testbench(vhdl)上交大testbench(vhdl)GenerateLabel:forParameterNameinRangegenerate ConcurrentStatements...endgenerate[Label];Label:ifConditiongenerate ConcurrentStatements...endgenerate[Label];肥卫堪糟厘苯襄兔惺剁怔盘钵声慎优铣雹忙虑跪半嘲买衣墨烤说越豪柠蚕上交大testbench(vhdl)上交大testbench(vhdl)GenerateExample(3)Addera(0) a(1) a(2) … a(wid-1) b(0) b(1) b(2) … b(wid-1)sum(0) sum(1) sum(2) … sum(wid-1) carry………HAFAFAFAa(0) b(0) c_in(1)a(1) b(1) c_in(2) a(2) b(2) c_in(3)c_in(win-1) a(wid-1) b(wid-1)sum(0) sum(1) sum(2) sum(wid-1) carry…曳磺霄逛鳃宪衫术批顾刊傀流羡锌蔫薪姓襟荆矗跌八烤静歼孟菱一最窜曰上交大testbench(vhdl)上交大testbench(vhdl)GenerateExample(4)adder:foriin0towid-1generate ls_bit:ifi=0generate ls_cell:HA portmap(a(0),b(0),sum(0),c_in(1)); endgeneratelsbit; middle_bit:ifi>0andi<wid-1generate middle_cell:FA portmap(a(i),b(i),c_in(i),sum(i),c_in(i+1)); endgeneratemiddle_bit; ms_bit:ifi=wid-1generate ms_cell:FA portmap(a(i),b(i),c_in(i),sum(i),carry); en