文档介绍：华中科技大学
硕士学位论文
片上路由器及其可靠性的研究与容错设计
姓名:高唯天
申请学位级别:硕士
专业:软件工程
指导教师:雷鑑铭
2010-05-22
摘
随着半导体技术的飞速发展,单个芯片上集成的 IP 核数量将越来越多。而
基于片上总线的 SoC 在设计上遇到了全局时钟难以同步、地址空间有限、无法
支持多节点并行通讯以及系统扩展不够灵活等问题,严重制约了系统性能的提
高。片上网络(NoC)技术将计算机网络技术引入 SoC 的设计领域,从体系结
构上彻底解决了上述问题,并逐渐发展成为片上总线之外的一种新的通信结构,
成为该领域的研究热点。目前针对 NoC 的研究大部分集中在对拓扑结构、路由
器和路由算法等各个部件的性能优化方面。而随着系统复杂度的增加,可靠性已
成为必须研究的问题。对负责片上互连通信的路由器的可靠性的研究更是重要。
本文详细介绍了设计的基于 2D mesh 结构的片上路由器的组成结构,以及采
用的传输协议,并对片上路由器的故障进行了分类。基于并行计算机中常用的路
由技术,以及分布式系统中采用的容错技术,结合片上路由器的特点,提出一种
基于 2D mesh 拓扑结构的可重构片上路由器的可靠性设计。使用后备路径机制对
路由节点、网络接口及链路等进行容错设计,当所有路由节点均故障时,系统仍
能进行通信。以较小的硬件开销的代价,换取了片上网络系统可靠性较大的提高。
并分析了相关的片上网络的容错路由算法,及本文设计采用的可避免死锁的路由
算法。使用 Java 语言编写的 gpNoCsim 模拟器对设计进行建模及仿真,并对结
果进行分析,评估容错性设计对片上路由器可靠性的提高程度。

关键词:片上路由器,片上网络,可靠性,容错设计,路由算法
I
Abstract
With the rapid development of semiconductor technology, more and more IP
cores will be integrated on one single chip. But the chip bus based SoC design
encounters many problems, such as hard to synchronize the global clock, address
space is limited, cannot support multi-node munications, as well as the
system expansion is not flexible enough. All these problems seriously restricted the
improvement of the system performance. Network on chip (NoC) technology
work technology into SoC design field, completely solved the
above problems from architecture, gradually developed into a munication
structure besides the chip bus, and became a new research hotspot in the field. Most
of the current researches for NoC focus on optimizing the performance of the
topology, routers and routing algorithm. But as the plexity increases,
reliability has e a problem must be studied. Routers are responsible for on-chip
communications, so the reliability research for them is more important.
This paper described the design of position and transport protocol of the
on-chip router based on the 2D mesh structure, and classified the faults in the on-chip
router as we