多码率LDPC码编译码器的FPGA实现.doc

文档介绍：
多码率 LDPC 码编译码器的 FPGA 实现
唐兴国,魏东兴**
(大连理工大学信息与通信工程学院,辽宁大连 116024)
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摘要:本文提出了多码率低密度校验码(Low Desity Parity Check codes,LDPC 码)编译码
器的 FPGA 实现方案。采用优化 Efficient 编码算法提出了 LDPC 码编码器的结构,优化了
校验码元计算模块和存储模块的实现。利用改进归一化最小和算法提出了 LDPC 码译码器结
构,该结构采用了半并行计算方式和提前检测技术,并复用了存储模块和迭代计算模块。本
文采用硬件描述语言,使用上述优化算法在 FPGA 上进行了实现。实现结果表明,码长为
1944 的编码器能够有效支持四种码率,FPGA 硬件资源消耗低,最大编码吞吐率为 ;
译码器可有效支持四种码率,并能够在资源消耗和译码吞吐率性能之间取得较好的折中。
关键词:LDPC;FPGA;编译码器;多码率;高吞吐率
中图分类号:
Implementation of Encoder and Decoder for Multi-rate
LDPC Codes Based on FPGA
TANG Xingguo, WEI Dongxing
(School of Information munication Engineering, Dalian University of Technology,
LiaoNing DaLian 116024)
Abstract: This paper presents an implementation scheme of multi-rate Low Density Parity Check
(LDPC) codes Encoder and Decoder. Architecture of LDPC codes encoder is proposed, and the
module of check code calculation and the module of storage are optimized. Structure of LDPC
codes decoder is proposed. The structure uses semi-puting mode and early detection
technology, and shares the module of storage and the module of iterating calculation. Encoder and
decoder are implemented based on FPGA using hardware description language according to the
optimized algorithm. Implementation results show that the 1944 code-length encoder can
effectively support four code rates with low FPGA hardware resource