多元QC-LDPC快速编码器的FPGA实现.doc

文档介绍：
多元 QC-LDPC 快速编码器的 FPGA 实现#
何龙华,周相超,赵旦峰**
(哈尔滨工程大学信息与通信工程学院,哈尔滨 150001)
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摘要:多元 LDPC 码具有消除短环的能力,可以获得更好的纠错能力和抗突发错误的能力。
但编码复杂度限制了其实用化,为了实现多元 LDPC 码的快速编码,准循环(Quasi-Cyclic,
QC)结构的多元 LDPC 码被提出。多元 QC-LDPC 码的校验矩阵和生成矩阵都是由大小相同的
循环矩阵构成,在其运算过程中,多个子矩阵可以同时进行计算,而且在实现的时候只需要
存储每个子矩阵的生成元。本文针对多元 LDPC 码的特殊性进行分析,提出基于 SRAA 电路结
构的快速编码方法,并采用 FPGA 平台进行硬件实现,验证了本方法的可行性和高效性。
关键词:多元 LDPC 码;准循环结构;SRAA;FPGA
中图分类号:
The FPGA Implementations of efficient encoder for
nonbinary QC-LDPC
He Longhua, Zhou Xiangchao, Zhao Danfeng
(College of Information munication Engineering, Harbin Engineering University, Harbin,
150001)
Abstract: Non-binary LDPC code has a reduced probability of forming short cycles. They can
achieve good error correction performances and they are effective bating noise bursts.
However, plexity of non-binary LDPC coding restricted its practicality. In order to achieve
fast non-binary LDPC coding, quasi-cyclic non-binary LDPC coding structure is introduced,
parity-check matrix and generator matrix of QC-LDPC codes posed of the same size loop
matrix. Many operator matrices can be calculated simultaneously during operations. It is only
necessary to store each operator matrix generator as implementation. The particularity of
non-binary LDPC codes is analyzed in this paper. fast encoding method based on SRAA circuit
structure is proposed,