文档介绍：--------------------------------------------------------------VHDLKeyPadScanner--2004102218023--CreatedBy"DXPVHDLGenerator"--"Copyright(c2002-2004PurPerLimited"--------------------------------------------------------------------------------------------------------------------------VHDLKeyPadScanner------------------------------------------------------------LibraryIEEE;;EntityKeypadScannerIsport(CLK_1MHZ:InSTD_LOGIC;--ObjectKind=Port|PrimaryId=CLK_1MHZCOL:InSTD_LOGIC_VECTOR(3downto0;--ObjectKind=Port|PrimaryId=COL[3..0]KEY:OutSTD_LOGIC_VECTOR(3downto0;--ObjectKind=Port|PrimaryId=KEY[3..0]ROW:OutSTD_LOGIC_VECTOR(3downto0;--ObjectKind=Port|PrimaryId=ROW[3..0]RST:InSTD_LOGIC;--ObjectKind=Port|PrimaryId=RSTVALIDKEY:OutSTD_LOGIC--ObjectKind=Port|PrimaryId=VALIDKEY;attributeMacroCell:boolean;attributePART_NAME:string;attributePART_NAMEofKeypadScanner:Entityis"xc2s200epq208-5";EndKeypadScanner;------------------------------------------------------------------------------------------------------------------------ponentAND4S--ObjectKind=Part|PrimaryId=U12|SecondaryId=1port(I0:inSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U12-I0I1:inSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U12-I1I2:inSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U12-I2I3:inSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U12-I3O:outSTD_LOGIC--ObjectKind=Pin|PrimaryId=U12-O;ponentCB2CEB--ObjectKind=Part|PrimaryId=U22|SecondaryId=1port(C:inSTD_LOGIC;--ObjectKind=Pin|PrimaryId=E:inSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U22-CECEO:outSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U22-CEOCLR:inSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U22-CLRQ:outSTD_LOGIC_VECTOR(1downto0;--ObjectKind=Pin|PrimaryId=U22-Q[1..0]TC:outSTD_LOGIC--ObjectKind=Pin|PrimaryId=U22-TC;ponentCDIV4--ObjectKind=Part|PrimaryId=U26|SecondaryId=1port(CLKDV:outSTD_LOGIC;--ObjectKind=Pin|PrimaryId=U26-CLKDVCLKIN:inSTD_LOGIC--ObjectKind=Pin|PrimaryId=U26-CLKIN;ponentCDIV64--ObjectKind=Part|PrimaryId=U24|SecondaryId=1port(CL