文档介绍：ic Programming and Evolvable Machines, 2, 33–60, 2001
© 2001 Kluwer Academic Publishers. Manufactured in herlands.
A High-Performance, Pipelined, FPGA-Based
ic Algorithm Machine
BARRY SHACKLEFORD barry ******@hpl.
Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA 94304 .
GREG SNIDER greg ******@hpl.
Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA 94304 .
RICHARD J. CARTER dick ******@hpl.
Hewlett-Packard Laboratories, 1501 Page Mill Road, Palo Alto, CA 94304 .
ETSUKO OKUSHI ******@
Mitsubishi Electric Corporation, 5-5-1, Ofuna, Kamakura, Kanagawa 247-8501 Japan
MITSUHIRO YASUDA ******@
Mitsubishi Electric Corporation, 5-5-1, Ofuna, Kamakura, Kanagawa 247-8501 Japan
KATSUHIKO SEO ******@
Mitsubishi Electric Corporation, 5-5-1, Ofuna, Kamakura, Kanagawa 247-8501 Japan
HIROTO YASUURA ******@-
Kyushu University, Kasuga-shi 816 Japan
Received July 19, 2000; Revised October 18, 2000
Abstract. Accelerating a ic algorithm (GA) by implementing it in a reconfigurable field programm-
able gate array (FPGA) is described. The implemented GA features: random parent selection, which
conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter
child chromosomes over their less-fit parent chromosomes, which promotes evolution. child chro-
mosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover,
mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to main-
tain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can
be plurally implemented to maintain evaluated-chromosome throughput of one per clock cycle.
Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip imple-
mentation, running ata1MHzclock rate, that solves