文档介绍：RTL Coding and Optimization Guide for use with Design
Compiler
Jack Marshall
Tera Systems Inc.
jackm@
ABSTRACT
My career at Synopsys spanned 9 years and was focused entirely on front-end design. With each
new position within pany (FAE, Trainer, Consultant, Manager) I learned more about high
level design, coding styles, synthesis, scripting, optimization techniques, timing closure, timing
convergence and QoR. What I have noticed about the industry today, is that it is focused on the
wrong end of the development cycle. Fixing timing problems with better placement technology
is more of a last ditch effort than a state of the art approach. Ultimately, if the problem can’t be
fixed with placement – the designer has to go back to their RTL code and re-write it to fix the
problem. Code it correctly from the beginning, anticipating implementation roadblocks and
barriers, and you won’t need the big fancy tools to solve your timing convergence/closure
problems later in the design cycle.
Introduction
Your ess directly depends on your RTL description. What I have tried to do with this paper
is talk about what is involved to produce a good RTL description of a design. It’s not just
writing with good style. I have put together my lessons learned, favorite coding styles, rules of
thumb and optimization techniques, into a sort of guidebook for essful RTL synthesis.
1. essful Synthesis
Engineers are always in a hurry. They want answers, but they don’t want to spend time to figure
out the answers. Synthesis is the transformation of an idea from one format (list) into
another (gate-list) with optimization for improving speed or reducing area. A design has
the same function before and after synthesis. Treating synthesis/piler like a black
box without understanding what goes on inside is wrong. Your ess with piler is
directly related to your RTL code and how it intera