文档介绍：NANO, QUANTUM AND PUTING
Nano, Quantum and
puting
Implications to High Level Design and
Validation
Edited by
Sandeep K. Shukla
Virginia Polytechnic and State University,
Blacksburg, .
and
R. Iris Bahar
Brown University,
Providence, .
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 1-4020-8068-9
Print ISBN: 1-4020-8067-0
©2004 Springer Science + Business Media, Inc.
Print ©2004 Kluwer Academic Publishers
Dordrecht
All rights reserved
No part of this eBook may be reproduced or transmitted in any form or by any means, electronic,
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Sandeep dedicates this book
to his mother Atashi,
grandmother Nirupama, and
brother Rajiv. Iris dedicates
this book to her husband
Andrew and daughters
Jasmine and Maya, who
provide endless support even
with her crazy work
schedule.
Contents
Dedication v
Preface xi
Foreword xv
Acknowledgments xvii
Part I puting at the Physical Layer
Preface 3
1
Nanometer Scale Technologies: Device Considerations 5
Arijit Raychowdhury and Kaushik Roy
. Introduction 5
. Silicon Nanoelectronics 6
. Carbon Nanotube Electronics 11
. Molecular Diodes and Switches 27
. Conclusion 29
References 29
Part II Defect Tolerant puting
Preface 37
2
puting in the Presence of Defects and Faults: A Survey 39
Paul Graham and Maya Gokhale
. Background 40
. Error Detection, Masking, and Reconfiguration 42
. Non-puting Models and Architectures 58
. Tools 64
. Summary 66
References 67
3
Defect Tolerance at the End of the Roadmap 73
Mahim Mishra and Seth C. Goldstein
. Approaches for Achieving Defect Tolerance in the Nanometer Do-
main 76
viii NANO, QUANTUM AND PUTING
. Technology 78
. Toolflow Required to Achieve Defe