文档介绍：TITLE PAGE
SUBMICRON PONENTS FOR PLL-
BASED FREQUENCY SYNTHESIS
by
SYED IRFAN AHMED, .(ELECTRICAL),
. UNIVERSITY OF ENGG.&TECH., KARACHI,PAKISTAN
A thesis submitted to the Faculty of Graduate Studies and Research in
partial fulfillment of the requirements for the degree of
Master of Applied Science
Ottawa-Carleton Institute for Electrical Engineering
Department of Electronics
Carleton University
Ottawa, Ontario
August, 2002
Copyright 2002, Syed Irfan Ahmed
Acceptance
The undersigned mend to the Faculty of Graduate
Studies and Research, the acceptance of the thesis
“Submicron ponents for PLL-based
Frequency Synthesis”
submitted by Syed Irfan Ahmed, B. Eng.,
in partial fulfillment of the requirements for the degree of
Master of Applied Science
Thesis Supervisor
Chair, Department of Electronics
Carleton University
August, 2002
Abstract
This thesis presents the design, the design methodology and the submicron imple-
mentation of a PLL-based integer-N frequency synthesizer with an external loop-filter. The
synthesizer is implemented in µm, TSMC, digital CMOS process. The frequency
range is from 10 MHz to 300 MHz and the intended applications of this work are in the
areas of Systems-on-Chip, clock generation, networking and audio/video systems. The
acquisition time of an integer-N PLL-based synthesizer is primarily affected by the small
loop-bandwidth required to improve the spectral purity of the output tone. A novel phase-
frequency detector is presented that, in conjunction with the proposed acquisition-aiding
methodology, can shorten the acquisition time by a factor of to an unaided
acquisition scenario. To set up the discussion of the proposed acquisition-aiding method,
an analysis of ponents that make up the total acquisition time is given from control-
systems theory and PLL literature. Some acquisition-aiding techniques pared. The
circuits used to achieve such reduction in acqu