文档介绍：ESD Circuit Synthesis and Analysis Using TCAD and SPICE
John Rodriguez, Michael C. Smayling, and William L. Wilson"
Texas Instruments
Houston, Texas. USA
*Electrical puter Engineering Department, Rice University
Houston, Texas, USA
Abstract bination. The N+ resistor allows the internal
voltage to be clamped to the drain junction breakdown level
This paper describes the development of a SPICE sub-circuit of 15V, which is sufficient to protect the gate oxide, even
model for an avalanche triggered SCR used for ESD though the pad voltage may exceed this value. The Human
protection. The approach for developing the model is Body Model (HBM) ESD failure threshold for this device is
presented, including the extensive use of TCAD tools, which above 6KV.
provides physical insight. This is the first SPICE model
presented for an avalanche triggered SCR demonstrating
accurate terminal behavior under both steady state and
WELL
transient triggering conditions. It is intended for use in a
design environment for examining ESD circuit behavior at I
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the clip level. I --I-
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Introduction ! 1-'
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Design of ESD protection circuits is an important part of y- 4-
product development. From a process development view, the !
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challenges posed by the trends in advanced technologies ii
include the thinning of the gate o