文档介绍：ContentsMain PageTable of contentCopyrightAbout the AuthorList of FiguresList of TablesList of ExamplesForewordPrefaceWho Should Use This BookHow This Book anizedConventions Used in This BookAcknowledgmentsPart 1: Basic Verilog TopicsChapter 1. Overview of Digital Design with Verilog Evolution puter-Aided Digital Emergence of Typical Design Importance of Popularity of Verilog Trends in HDLsChapter 2. Hierarchical Modeling Design 4-bit Ripple Carry of a ExercisesChapter 3. Basic Lexical Data System Tasks piler ExercisesChapter 4. Modules and ModulesABC Amber CHM Converter Trial version, cesstext/ Hierarchical ExercisesChapter 5. Gate-Level Gate Gate ExercisesChapter 6. Dataflow Continuous Expressions, Operators, and Operator ExercisesChapter 7. Behavioral Structured Procedural Timing Conditional Multiway Sequential and Parallel Generate ExercisesChapter 8. Tasks and Differences between Tasks and ExercisesChapter 9. Useful Modeling Procedural Continuous Overriding pilation and Time ScalesABC Amber CHM Converter Trial version, cesstext/ Useful System ExercisesPart 2: Advanced VerilogTopicsChapter 10. Timing and Types of Delay Path Delay Timing Delay Back- ExercisesChapter 11. Switch-Level Switch-Modeling Sum