文档介绍：ABC Amber CHM Converter Trial version, cesstext/
Contents
Main Page
Table of content
Copyright
About the Author
List of Figures
List of Tables
List of Examples
Foreword
Preface
Who Should Use This Book
How This Book anized
Conventions Used in This Book
Acknowledgments
Part 1: Basic Verilog Topics
Chapter 1. Overview of Digital Design with Verilog HDL
Evolution puter-Aided Digital Design
Emergence of HDLs
Typical Design Flow
Importance of HDLs
Popularity of Verilog HDL
Trends in HDLs
Chapter 2. Hierarchical Modeling Concepts
Design Methodologies
4-bit Ripple Carry Counter
Modules
Instances
of a Simulation
Example
Summary
Exercises
Chapter 3. Basic Concepts
Lexical Conventions
Data Types
System Tasks piler Directives
Summary
Exercises
Chapter 4. Modules and Ports
Modules
ABC Amber CHM Converter Trial version, cesstext/
Ports
Hierarchical Names
Summary
Exercises
Chapter 5. Gate-Level Modeling
Gate Types
Gate Delays
Summary
Exercises
Chapter 6. Dataflow Modeling
Continuous Assignments
Delays
Expressions, Operators, and Operands
Operator Types
Examples
Summary
Exercises
Chapter 7. Behavioral Modeling
Structured Procedures
Procedural Assignments
Timing Controls
Conditional Statements
Multiway Branching
Loops
Sequential and Parallel Blocks
Generate Blocks
Examples
Summary
Exercises
Chapter 8. Tasks and Functions
Differences between Tasks and Fun