文档介绍：SystemVerilog讲座第一讲::GatewayDesignAutomation推出Verilog初版1989:Gateway被CadenceDesignSystems公司收购1990:Cadence向业界公开VerilogHDL标准1993:OVI提升theVerilog标准,但没有被普遍接受1995:IEEE推出VerilogHDL(IEEE1364-1995)标准2001:IEEE推出VerilogIEEEStd1364-2001标准2002:-2002标准2002:–Accellera是OVI&VHDLInternational(VI)合并后的国际标准化组织2003::?-IEEE1364-1995“Verilog-1995”标准–-IEEE1364-2001“Verilog-2001”标准–第二代IEEEVerilog标准–显著提升了Verilog--国际标准化组织对Verilog-2001的扩展–第三代Verilog标准–DAC-2002-–DAC-2003-是Verilog-2001扩展后的超集assertionsmailboxestestprogramblockssemaphoresclockingdomainsconstrainedrandomvaluesprocesscontroldirectCfunctioncalls-----------------------SystemVerilog------------------------------------fromC/C++--------是Verilog-2001扩展后的超集interfacesdynamicprocessesnestedhierarchy2-statemodelingbyteunrestrictedportspackedarraysimplicitportconnectionsarrayassignmentsenhancedliteralsenhancedeventcontroltimevalues&unitsunique/prioritycase/iflogic-specificprocessesrootnamespacealiasconst&=|=^=%=--------------------------------------------------------------fromC/C++--------intglobalsbreakshortintenumcontinuelonginttypedefreturnBytestructuresdo-whileShortrealunions++--+=-=*=/=voidcasting>>=<<=>>>=<<<=aliasconst&=|=^=%=-------------------------SystemVerilog-------------------------------是Verilog-2001扩展后的超集ANSICstyleportsstandardfileI/O(*attributes*)generate$value$plusargsconfigurationslocalparam`ifndef`elsif`linememorypartselectsconstantfunctions@*variablepartselect--------fromC/C++--------multidimensionalarrayssignedtypesAutomatic**(poweroperator)----------------------------------Verilog-2001----------