文档介绍：ADC RF_P,N Program Flash 128/192 kB Data RAM 12 kB HF crystal OSC LF crystal OSC General Purpose ADC Serial Wire and JTAG debug Internal LF RC-OSC GPIO multiplexor switch Chip manager Regulator Bias 2 level Interrupt controller RF_TX_ALT_P,N OSCA OSCB PA[7:0], PB[7:0], PC[7:0] Encryption acclerator IF Always Powered Domain ARM Cortex -M3 CPU with NVIC and MPU VREG_OUT Watchdog LNA PA PA DAC MAC + Baseband Sleep timer POR nRESET General purpose timers GPIO registers UART/ SPI/TWI SYNTH Internal HF RC-OSC SWCLK, JTCK Calibration ADC CPU debug TPIU/ITM/ FPB/DWT Regulator VDD_CORE EM351 / EM357 High-Performance, Integrated ZigBee/ System-on-Chip ? Complete System-on-Chip ? 32-bit ARM ? Cortex ?-M3 processor ? GHz IEEE -2003 transceiver & lower MAC ? 128 or 192 kB flash, with optional read protection ? 12 kB RAM memory ? AES128 encryption accelerator ? Flexible ADC, UART/SPI/TWI serial communications, and general purpose timers ? 24 highly configurable GPIOs with Schmitt trigger inputs ? Industry-leading ARM ? Cortex ?-M3 processor ? Leading 32-bit processing performance ? Highly efficient Thumb-2 instruction set ? Operation at 6, 12, or 24 MHz ? Flexible Nested Vectored Interrupt Controller ? Low power consumption, advanced management ? Rx Current (w/ CPU): 26 mA ? Tx Current (w/ CPU, +3 dBm TX): 31 mA ? Low deep sleep current, with retained RAM and GPIO: 400 nA without/800 nA with sleep timer ? Low-frequency internal RC oscillator for low- power sleep timing ? High-frequency internal RC oscillator for fast (110 μsec) processor start-up from sleep ? Exceptional RF Performance ? Normal mode link budget up to 103 dB; configurable up to 110 dB ?-100 dBm normal RX sensitivity; configurable to -102 dBm (1% PER, 20 byte packet) ?+3 dB normal mode output power; configurable up to +8 dBm ? Robust Wi-Fi and Bl uetooth coexistence ? work and processor debug ? Ember InSight po