文档介绍：DESIGN OF A DVB-S RECEIVER IN FPGA
Francisco Curdells-Tormo'. Asun Pirez-Pascuu12. Vicente Torres-Carol.
Javier Valls-Coquillu12, and Vicenc Alrnenar-Terrk'
'mercial Division (ICD) R&D Lab, Hewlett-Packard
OX 190 Sant Cugat del Valles, Barcelona, Spain -torrno@
Department of Electronic Engineering, Polytechnic University of Valencia (UPV),
Ctra Nazaret-Oliva s/n, 46730 Grao de Gandia, Valencia, Spain {}(
'Department of munications, Polytechnic University of Valencia (UPV),
Ctra Nazaret-Oliva s/n, 46730 Grao de Gandia, Valencia, Spain valmenar@,
bandwidth limitations.
In this work we are going to study three different
case studies for the receiver. Two of them will use
ABSTRACT 70 MHz as the intermediate frequency and the other one
140 MHz. In the data acquisition we will employ
This paper deals with the design of an all-digital receiver passband sampling in two of them and low pass sampling
for the DVB-S standard in FPGA. We describe the in the other one.
implementation issues of the next stages: digital The structure of this paper is as follows. First we will
acquisition at intermediate frequency, downconversion to present a receiver architecture suitable for FPGAs. After
baseband, synchronization in time, and synchronization in this, each building block is explained