文档介绍：FEATURE THE PROJECT
Building a panies sell FPGA CPU
cores, but most are synthesized imple-
ARTICLE mentations of existing instruction
RISC sets, filling huge, expensive FPGAs,
and are too slow and too costly for
production use. These cores are mar-
Jan Gray keted as ASIC prototyping platforms.
System in In contrast, this article shows how
a streamlined and thrifty CPU design,
optimized for FPGAs, can achieve a
an FPGA cost-effective puter
system, even for low-volume products
that can’t justify an ASIC run.
I’ll build an SoC, including a 16-bit
RISC CPU, memory controller, video
Part 1: Tools, Instruction Set, and Datapath display controller, and peripherals, in
a small Xilinx 4005XL. I’ll apply free
software tools including a piler
and assembler, and design the chip
using Xilinx Student Edition.
If you’re new to Xilinx FPGAs, you
used to envy can get started with the Student Edi-
i CPU designers— tion . This package includes the
the lucky engineers development tools and a textbook
To kick off this three- with access to expensive with many lab exercises.[3]
tools and fabs. But, field-program- The Xilinx university-program
part article, Jan’s go- mable gate arrays (FPGAs) have made folks confirm that Student Edition is
custom-processor and integrated- not just for students, but also for pro-
ing to port a C system design much more accessible. fessionals continuing their education.
20–50-MHz FPGA CPUs are per- Because it is discounted with respect
compiler, design an fect for many embedded applications. to mercial products, you do
They can support custom instructions not receive telephone support, al-
instruction set, write and function units, and can be recon- though there is web and fax-back
figured to enhance system-on-chip support. You also do not receive
an assembler and (SoC) development, testing, debug- maintenance updates—if you need the
ging, and tuning. Of course, FPGA
simulator, and desi