文档介绍：Presented at GNSS 2005
The 2005 International Symposium on GNSS/GPS
Hong Kong
8-10 December 2005
FPGA based GPS receiver design considerations
K J Parkinson, A G Dempster, P Mumford, C Rizos
Satellite Navigation and Positioning Group
School of Surveying and Spatial Information Systems
University of New South Wales
Sydney NSW 2052 Australia
E-mail: k.******@
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Presenter: Andrew Dempster
ABSTRACT
A project to build a GPS receiver using an FPGA for base-band processing began in
2004. The new receiver platform uses monly available RF front end ASIC to
convert the GPS signals to a suitable IF. The digital design for baseband processing
is normally a reasonably straight forward task. However, because the received GPS
signals are at such low levels this presents some challenges. One of the main
considerations is to avoid contamination of the ing signals with interference
that can be generated from the digital electronics when using an FPGA. In this paper
we describe the hardware design process with a focus on avoiding interference while
still plex FPGA logic to operate alongside sensitive GPS RF signal
processing.
KEYWORDS: FPGA, GPS Receiver, CDMA.
1. INTRODUCTION
As outlined previously [1], this project to build a GPS receiver using an FPGA for the base-
band processing