文档介绍：ABSTRACT
Sparse Matrix-Vector Multiplication is putation kernel in many engineering and scientific
computation. With the extensive use of FPGA, some in-depth research have been done on SMVM
based FPGA. By using the parallelism of FPGA, some researchers have designed putation
architecture of SMVM by hardware logic and achieved putational performance. But there
are few ings on putation architecture, ings are about low utilization of
chip resources and poor flexibility. In this paper, the typical architecture based hardware logic has
been optimized by using the idea of hardware and software co-design. At last puting
architecture based multi-core added with co-processing unit has been designed and used it to
implement puting system.
First, the background and profile of research on SMVM are introduced. And then this paper
introduces the basic concepts involved in SMVM. Through introducing FSL bus extension of the
Microblaze soft core processor, this paper introduces a method of realizing hardware acceleration
and multi-core by FSL bus. The binary puting architecture which contains four multipliers
has been optimized through analyzing on the binary puting architecture which is realized
by hardware logic. And then puting architecture based multi-core added with co-processing
unit is given. During the optimization process, the position method is used. And this paper
also introduces one method of multiple processors controlling the co-processing unit. Hardware can
be called by software by using this method. At last, puting system is realized by using
computing architecture based multi-core added with co-processing unit, and this paper also gives
some results about this puting system through simulation analysis

Key words: FPGA, Sparse Matrix-Vector Multiplication, Multi-core, Co-processing unit

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南京邮电大学学位论文原创性声明
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