文档介绍：NANA: A Nano-scale work Architecture JAIDEV P. PATWARDHAN Department puter Science, Duke University. CHRIS DWYER Department of Electrical puter Engineering, Duke University. ALVIN R. LEBECK Department puter Science, Duke University, DANIEL J. SORIN Department of Electrical puter Engineering, Duke University. ________________________________________________________________________ This paper explores the architectural challenges introduced by emerging bottom-up fabrication of nanoelectronic circuits. The specific nanotechnology we explore proposes patterned DNA nanostructures as a scaffold for the placement and interconnection of carbon nanotube or silicon nanorod FETs to create a limited size circuit (node). Three characteristics of this technology that significantly impact architecture are 1) limited node size, 2) random node interconnection, and 3) high defect rates. We present and evaluate an accumulator-based work architecture that patible with any technology that presents these three challenges. This architecture represents an initial, unoptimized solution for understanding the implications of DNA-guide self-assembly. Categories and Subject Descriptors: [Hardware]: Arithmetic and Logic Structures – Design Styles; [Hardware]:Input/Output and munications - Interconnection Subsystems; [Hardware] Logic Design – Design Styles; [Hardware] : Integrated Circuits – Types and Design Styles; anization]: General; anization]: Processor Architectures – Other Architecture Styles General Terms: Design, Performance Additional Key Words and Phrases: accumulator ISA, work, carbon nanotube, DNA, defect isolation, defect tolerance, puting, nanoelectronics, reverse path forwarding, self-assembly. ________________________________________________________________________ 1. INTRODUCTION The semiconductor industry’s roadmap identifies a “red brick wall” beyond which it is unknown how to extend the historical trend of ever-decreasing CMOS devi