文档介绍：Vol. 31, No. 11 Journal of Semiconductors November 2010
Selecti onto the SiO2 interface layer by co-sputtering
Œ1
metal–oxide–semiconductor (CMOS) technologies . Replac- of Hf and Si targets in an Ar/N2 ambience. A TaN metal gate
ing poly gate electrodes with dual metal gates with work func- was deposited on the HfSiON that annealed by rapid thermal
tions near the band-edges of Si can eliminate poly deple- annealing (RTA) at 900 ıC for 30 s through reactive sputter-
Œ2 4
tion, boron penetration and Fermi level pinning
. Replac- ing of the Ta target in Ar/N2 ambient. Then the a-Si hardmask
ing SiO2 or SiON gate dielectrics with high-k gate dielectrics was deposited by LPCVD at 550 ıC and etched with a Cl2/HBr
can reduce the gate direct tunneling leakage current and power gas mixture in a LAM Rainbow 4420, which is a plasma etch-
consumptionŒ2; 4. A versatile method of integrating dual metal ing system with 4 inch wafers. Wet etches were performed in a
gate CMOS is to employ a metal wet etch process to selectively beaker set-up by immersing the sample into the etch solution.
remove the first metal from either the NMOS or PMOS region After etching, samples were rinsed in deionized water ten times
before depositing the second me