文档介绍：西安邮电学院可编程逻辑实验报告实验名称八、计数器设计一:实验目的 1 .掌握计数器电路设计的方法。 2 .通过开发 CPLD 来实现时序逻辑电路的功能。二:实验所用仪表及主要器材 MAX+PLUSII 软件等三:实验原理简述(源程序、真值表、原理图) 模 24 计数器源程序: library ieee; use ; use ; entity e8_ counter is port(en:in std_logic; clear:in std_logic; clk:in std_logic; cout:out std_logic; qd1,qd0,qs3,qs2,qs1,qs0:out std_logic); end e8_ counter; architecture f2 of e8_ counter is signal counter_h: std_logic_vector(1 downto 0); signal counter_l: std_logic_vector(3 downto 0); begin cout<='1' when(counter_h="10" and counter_l="0011" and en='1')else '0'; process(clk,clear) begin 系别通信系学号Xxxxxxxx 成绩实验日期 2009-12-13 班级通工 0702 姓名高原教师签字 if(clear='1')then counter_h<="00"; counter_l<="0000"; elsif(clk'event and clk='1')then if(en='1')then if (counter_h="10" and counter_l="0011")then counter_h<="00"; counter_l<="0000"; elsif(counter_l="1001")then counter_l<="0000"; counter_h<=counter_h+1; else counter_l<=counter_l+1; end if; end if; end if; end process; qd0<=counter_h(0); qd1<=counter_h(1); qs0<=counter_l(0); qs1<=counter_l(1); qs2<=counter_l(2); qs3<=counter_l(3); end f2; 真值表: enC lk clear Q s3Q s2Q s1Q s0Q d1Q d0 count 0↑10000000 1↑00000000 1↑00001000 1↑00011000 1↑00010000 1↑00110000 1↑00101000 1↑00101000 1↑01100000 1↑01010000 1↑01011010 1↑0