文档介绍：Hot Carrier Reliability of N-LDMOS Transistor Arrays
for Power BiCMOS Applications
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Douglas Brishin*, Andy Strachan, Prasad Chaparala
National Semiconductor Corporation .
2900 Semiconductor Drive, Santa Clara CA 95052-8090
*(408) 721-3642, Fax (408) 721-6454, @
To obtain high "rrents and minimal Rdson, LDMOS
devices are often implemented in a checkerboard array of transistors.
ABSTRACT '3.
Figure. 2 depicts a schematic view of an 8 source LDMOS array.
Transistor arrays posed of unit cells consisting of a single
of
This paper evaluates the hot carrier performance n-channel source and drain. Metal routing ties all sources (and drains) together
lateral DMOS (N-LDMOS) transistors. The N-LDMOS has been the
creating a parallel device sbucture. A separate connection to the
common choice for the driver transistor in high voltage (20-30 V)
polysilicon gate controls the resistance of the device. Advantages of
malt power applications. These high +in voltages potentially transistor arrays include high current capability with minimum power
make N-LDMOS hot carrier degradation an important reliability
dissipation and more uniform cument flow per device area.
concem. This paper focuses on the hot carrier test methodology and
geometry effects in N-LDMOS transistor arrays. This paper differs
from previou