文档介绍：Library ieee;
Use ;
Use ;
Use ;
Entity topadapt port map(en=>en,h1=>h1,clk=>e,minin=>c,hourset=>d);
u6:deled port map(num=>m0,led=>ledout);
u7:div1hz1 port map(clk1=>clk1,cl=>f1);
u8:settime port map(clk2=>f1,n0=>d0,n1=>d1,n2=>d2,n3=>d3,n4=>d4,n5=>d5,
daout=>m0,sel=>sel,dp=>dp);
end;
LIBRARY ieee;
use ;
use ;
ENTITY deled IS
PORT(num:IN std_logic_vector(3 downto 0);
led:OUT std_logic_vector(6 downto 0));
end deled;
ARCHITECTURE fun OF deled IS
BEGIN
led<="1111110"when num="0000"else
"0110000"when num="0001"else
"1101101"when num="0010"else
"1111001"when num="0011"else
"0110011"when num="0100"else
"1011011"when num="0101"else
"1011111"when num="0110"else
"1110000"when num="0111"else
"1111111"when num="1000"else
"1111011"when num="1001"else
"1110111"when num="1010"else
"0011111"when num="1011"else
"1001110"when num="1100"else
"0111101"when num="1101"else
"1001111"when num="1110"else
"1000111"when num="1111";
END fun;
library ieee;
use ;
use ;
entity div1hz is
generic(n:integer:=50000000);
port(clk1:in std_logic;
clock:out std_logic);
end;
architecture a of div1hz is
signal count:integer range 0 to 49999999;
begin
process(c