文档介绍:cadence pcb设计与制板(Cadence PCB设计与制板)
Cadence PCB设计与制板笔记
1、安装§ :
spbl5. 2 CD1〜3,安装1、2,第3为库,不安装
许可证安装:
设置环境变量 lm_licensbels in the wrong place)
Check, hierarchical, port, connection (hierarchical port connection)
Check off-page connector connection (flat port connection)
Report identical part referenves (check duplicate element serial number)
Report invalid package (check invalid package)
Report, hierarchical, ports, and, off-page, connector (listing port and off-page connections)
Check unconnected net
Check SDT compatible
Report all net names
View output
ERC Matrix
Component Automatic Numbering (Tools\Annotate)
Scope:Update entire design/selection
Action;
Incremental/unconfitional reference update
Reset, part, reference, to?”
Add/delete Intersheet Reference (the serial number of the port on the paging paper plus / delete the number of the drawing)
Combined property
Reset, reference, numbers, to, begin, at, 1, each, page
Do, not, change, the, page, number
Automatically update device or network properties (Tools\Update, Properties,...)
Scope:Update entire design/selection
Action:
Use case inseneitive compares
Convert, the, update, property, to, uppercase
Ynconditionally update the property
Do, not, change, updated, properties, visibility
Make, the, updates, property, visible/invisible
Create a report file
Property update
Generate netlist (Tools\Create, Netlist,...), Allego, etc. 39 netlist before confirmation: component number, DRC check,
attribute data, and encapsulation
PCB Footprint (specifies the PCB encapsulation property name: PCB Footprint default), . . setup modifies, edits, and views files
Create Allegro netlist: generates network tables in Allegro, pstchip. dat, pstxnet. dat:
psdxprt. dat
option
netlist files:指定pst *. dat文件保存的位置,默认为在设计中 指定的最后一次调用对话框的目录.
第一次设计网络表,默认的位置为设计目录的allegro子文件,这 ,则默认的位置为用这个对话 框设计的最后使用的目录
view: 自动打开 pst *. dat.
create or update allegro)
生成元件清单(tools and bill of materials.
scop