文档介绍：ASICs...THE COURSE (1 WEEK)
ASIC LIBRARY 3
DESIGN
Key concepts: Tau, logical effort, and the prediction of delay • Sizes of cells, and their drive
strengths • Cell importance • The difference between gate-array macros, standard cells, and
datapath cells
ASIC design uses predefined and precharacterized cells from a library—so we need to
design or buy a cell library. A knowledge of ASIC library design is not necessary but makes
it easier to use library cells effectively.
Transistors as Resistors
–tPDf
= VDD exp –––––––––––––––––
Rpd (Cout + Cp)
An output trip point of is convenient because ln(1/)=»1 and thus
tPDf = Rpd(Cout + Cp) ln (1/) » Rpd(Cout + Cp)
For output trip points of we multiply by –ln() = , because exp (–) =
1
2 SECTION 3 ASIC LIBRARY DESIGN ASICS... THE COURSE
VDD
v(in1)
m2
VDD v(out1) t' =0
m2 VDD
–IDSp Rpu
VDD exp[–t' / (Rpd (Cp + Cout))]
in1 out1 in1 out1
m1 DD
m1
–(I + I ) Rpd
IDSn DSp DSn 0
tPDf t'
Cout C C C
t' =0 » Rpd (Cp + Cout) p out
t' =0
m1: off saturation linear
(a) (b) (c)
A linear model for CMOS logic delay
• Ideal switches = no delay • Resistance and capacitance causes delay
• Load capacitance, Cout • parasitic output capacitance, Cp • input capacitance, C
• Linearize the switch resistance • Pull-up resistance, Rpu • pull-down resistance, Rpd
• Measure pare the input, v(in1) and output, v(out1)
• Input trip point of • output trip points are (falling) and (rising)
• The linear prop–ramp model: falling propagation delay, tPDf » Rpd(Cp+Cout)
ASICs... THE COURSE Transistors as Resistors 3
(a) (b)
1
v(out1) / V
nonequilibrium path 1
3
max(IDSn, –IDSp) /mA nonequilibrium path
equilibrium
path
2 3 IDSn
v(in1) /V
3
1 IDSn=–IDSp
2
0 –IDSp
3
equilibrium 1
2 path
0
1
0 1 2 3 v(out1) / V 0 2
v(in1) /V 0
(c)
max(I –I ) /mA
DSn, DSp 2
C