文档介绍：IEEE TRANSACTIONS PONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, VOL. CHMT-4, NO. 2, JUNE 1981 181
CRAY-puter Technology
JAMES S. KOLODZEY, MEMBER, IEEE
Abstract-Hardware and packaging technology which provide the
high performance of the CRAY-puter are reviewed. A brief
overview of puter is given, followed by a description of the
computer circuits, packaging, power distribution, and cooling system.
I. INTRODUCTION
INCE ITS introduction in 1976, the CRAY-1 has developed
Sa reputation as a fast and reliable scientific processor. The
CRAY-lS, announced in 1979, offers enhanced input/output
(I/O) capability and an increase of the maximum memory size
from one million to four million words. A photo of the
CRAY-1S is shown in Fig. 1, where the large section at the
left contains the central processing unit (CPU) and memory,
and the smaller section at the right contains the I/O proc-
essor. Fig. 2 shows the CPU chassis layout and circuit module
locations. Data and control signal paths are given in Fig. 3. Fig. 1. CRAY-IS mainframe.
Applications for the CRAY-1 include large-scale calculations
of the type required in weather forecasting, petroleum and or operand pairs. By contrast, scalar processors perform one
earthquake seismology, structural analysis, nuclear engi- iteration on one or a pair of operands. Each operand has a
neering, and pa