文档介绍：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003 829
Phase-Noise Cancellation Design Tradeoffs in
Delta–Sigma Fractional-x PLLs
Sudhakar Pamarti and Ian Galton, Member, IEEE
Abstract—A theoretical analysis of a recently proposed phase-
noise cancellation technique that relaxes the fundamental tradeoff
between phase noise and bandwidth in fractional- phased-
locked loops (PLLs) is presented. The limits imposed by circuit er-
rors and PLL dynamics on the phase noise and loop bandwidth that
can be achieved by PLLs incorporating the technique are quanti-
fied. Design guidelines are derived that enable customization of the
technique in terms of PLL target specifications.
Index Terms—Delta–sigma modulator, fractional- PLL,
phased-locked loop (PLL), segmented digital-to-analog converter
(DAC), synthesizer.
I. INTRODUCTION
PHASE-NOISE cancellation technique is presented in [1] Fig. 1. A high-level functional diagram of the fractional-N PLL presented
A that employs a digital-to-analog converter (DAC) cancel- in [1].
lation path to suppress the phase noise arising from quantiza-
tion error in a delta-sigma fractional- phase-locked loop Section II presents an overview of the phase-noise cancella-
(PLL). The technique has been shown to allow a ten-fold in- tion technique and describes the var