文档介绍：基于CPLD的数字频率计的设计
摘要频率是电子技术中最基本的参数之一,与其他电参量的测量方案及结果关系非常密切。其中数字频率计在各方面领域都有很广泛的运用,随着科技的发展与生活的提高,数字频率计的需求也将大大提升。
目前直接测频方法有两种:测频法和测周期法。测频法是在确定的时间Tw内,记录被测信号的变化周期数Nx,则测得的频率为:fx=Nx/Tw。测周期法需有标准信号频率fs,在待测信号的一个周期Tx内,记录标准频率的周期数。则测得的频率为:fx=fs/Ns 。本课题主要选择以CPLD为核心器件,VHDL为编程语言,采用测频法设计一个简单实用的数字频率计,以计数器、译码器为核心,由内部分频输入信号、信息锁存、数字显示等功能模块组成,可以实现简单的频率测量。
关键词 CPLD,频率计,计数,仿真波形
ABSTRACT
Frequency of electronic technology in one of the most basic parameters, and other electrical parameters and results of the measurement scheme very which all aspects of digital frequency meter in the field have a very widely used, with the development of technology and life improved, the demand for digital frequency meter will also be greatly enhanced.
Direct measurement of the current frequency in two ways: frequency measurement method and test cycle method. Frequency measurement method is in determining the time Tw, the record number of cycles the signal changes in Nx, then the measured frequency is: fx = Nx / Tw. The need for standard test cycle approach signal frequency fs, a cycle in the Tx signal under test, The recorded number of cycles the standard frequency. The measured frequency is: fx = fs / Ns. The main subject chosen as the core device CPLD, VHDL as a programming language, frequency measurement method using a simple and practical design of digital frequency meter to counter, decoder core, from the inner part of the frequency of the input signal, the information is latched, figures show other functional modules, a simpl
e frequency measurement can be achieved.
Key Words:CPLD Frequency Counter Count Simulation waveform
目录
一、绪论 1
课题背景及其意义 1
设计背景 1
设计目标 1
设计意义 1
设计思路 2
软件方面 2
硬件方面 2
数字频率计的发展 2
数字频率计的分类 3
数字频率计的相关概念 4
数字频率计实现的主要方法 5
二、设计内容 7
三、设计方案步骤 8
信号输入 8
时基控制模块 8
分频器模块 9
计数器模块 9
锁存器模块 10
译码器模块 11
调试 11
软件调试 11
硬件调试 11
四、设计总结 13
五、参考文献 14
六、附录 15
附录1 总电