文档介绍：High Performance
works
Architectures, Algorithms, and Opportunities
Synthesis Lectures puter
Architecture
Editor
Mark D. Hill, University of Wisconsin
Synthesis Lectures puter Architecture publishes 50- to 100-page publications on topics
pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware
components to puters that meet functional, performance and cost goals. The scope will
largely follow the purview of puter architecture conferences, such as ISCA, HPCA,
MICRO, and ASPLOS.
High Performance works: Architectures, Algorithms, and Opportunities
Dennis Abts and John Kim
2011
puting for Architects, Second Edition
Tzvetan Metodi, Fred Chong, and Arvin Faruque
2011
Processor Microarchitecture: An Implementation Perspective
Antonio González, Fernando Latorre, and Grigorios Magklis
2010
Transactional Memory, 2nd edition
Tim Harris, James Larus, and Ravi Rajwar
2010
Computer Architecture Performance Evaluation Methods
Lieven Eeckhout
2010
Introduction to Reconfigurable puting
Marco Lanzagorta, Stephen Bique, and Robert Rosenberg
2009
On-works
Natalie Enright Jerger and Li-Shiuan Peh
2009
iii
The Memory System: You Can’t Avoid It, You Can’t Ignore It, You Can’t Fake It
Bruce Jacob
2009
Fault puter Architecture
Daniel J. Sorin
2009
The Datacenter as puter: An Introduction to the Design of Warehouse-Scale Machines
free access
Luiz André Barroso and Urs Hölzle
2009
Computer Architecture Techniques for Power-Efficiency
Stefanos Kaxiras and Margaret Martonosi
2008
Chip Multiprocessor Architecture: Techniques to Improve Throughput and Latency
Kunle Olukotun, Lance Hammond, and James Laudon
2007
Transactional Memory
James R. Larus and Ravi Rajwar
2006
puting puter Architects
Tzvetan S. Metodi and Frederic T. Chong
2006
Copyright © 2011 by Morgan & Claypool
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