文档介绍：AN07
Integrated
Circuit
Clock Generators Application
Systems, Inc.
General FTG PCB Layout mendations
Termination Power Bypassing
1. The series clock terminating resistor should be as close to With respect to bypassing the device the following is -
the clock source as physically possible. mended.
2. The value of this resistor must be such as to assist in A. A minimum .1 mF capacitor (low ESR ) placed as close to
matching the clock source to the load impedance. Most ICS each VDD pin as is physically possible is menced for
parts present an internal characteristic impedance of 20 to high frequency bypassing. Placing SMD bypass capacitors
30 ohms when in operation. To match this driver to a 50 on the opposite side of the board is an excellent method of
ohm transmission line (clock trace) we would mend minimizing the length of trace between the FTG’s power
using a 22 ohm series matching resistor. Based on the clock and the bypass capacitors pins.
traces actual characteristic, we also mend that you
observe the waveform and, if necessary, empirically deter- B. We mend that the FTG’s power pins be supplied
mine the absolute value fit for your application to bring the from a single power point. The power trace for each pin
ringing and levels into good design limits. should travel, on a separate trace for each device power pin,
Duty Cycle 1. from a single