文档介绍：基于vhdl电子密码锁设计说明书密码锁设计密码锁设计顶层电路图(2)顶层时序仿真分频模块(1)10分频程序libraryieee;;;entityyourname_div10isport(clk:instd_logic;co:outstd_logic);end;architecturebehavofyourname_div10issignalcount:std_logic_vector(3downto0);beginprocess(clk)beginifclk'eventandclk='1'thenifcount="1001"thencount<="0000";co<='1';elsecount<=count+1;co<='0';endif;endif;endprocess;endbehav;(2)5分频程序libraryieee;;;entityyourname_div5isport(clk:instd_logic;co:outstd_logic);end;architecturebehavofyourname_div5issignalcount:std_logic_vector(2downto0);beginprocess(clk)beginifclk'eventandclk='1'thenifcount="100"thencount<="000";co<='1';elsecount<=count+1;co<='0';endif;endif;endprocess;endbehav;(3)10分频时序仿真波形(4)5分频时序仿真波形从以上波形仿真可以看出该板块10分频模块的输出是输入信号的10分频,同理5分频的输出是输入信号的5分频。附录三:消抖模块(1)消抖模块程序libraryieee;;;entityyourname_xiaodouisport(clk_1k:instd_logic;keyin:instd_logic;keyout:outstd_logic);end;architecturebehavofyourname_xiaodouissignaln:integerrange0to29;beginprocess(clk_1k)beginifkeyin='1'thenn<=0;keyout<='1';elsifclk_1k'eventandclk_1k='1'thenifn<29thenn<=n+1;keyout<='1';elsen<=29;keyout<='0';endif;endif;endprocess;endbehav;(2)仿真波形附录四:输入模块(1);;;entityyourname_count10isport(clk:instd_logic;bcd:bufferstd_logic_vector(3downto0));end;architecturebehavofyourname_count10isbeginprocess(clk)beginifclk'eventandclk='1'thenifbcd="1001"thenbcd<="0000";elsebcd<=bcd+'1';endif;endif;endprocess;endbehav;;;entityyourname_kaiqiisport(clk:instd_logic;sel:instd_logic;input:instd_logic_vector(3downto0);output:outstd_logic_vector(3downto0));end;architecturebehavofyourname_kaiqiisbeginprocess(clk,sel)beginifsel='1'thenoutput<=input;elseoutput<="0000";endif;endprocess;endbehav;;