文档介绍：上海交通大学
硕士学位论文

姓名:方龙洋
申请学位级别:硕士
专业:软件工程
指导教师:施国勇
20070609
基于 piler 实现微米高性能 SRAM 之设计方法

摘要

近年来,很多 IP 设计供应商和芯片制造厂(Foundry)致力于开发存
储器编译器(piler),其核心竞争力在于面积和速度方面取得
优势,面对诸多的竞争对手,本文通过在同一存储器编译器中采用两种
SRAM 电路设计结构,打破了传统业界采用一种电路结构的局限,提出
了一种新的电路结构设计方法, 从而使本设计的存储器编译器达到面
积、速度的优化,面积比业界小 20%,速度比业界快 15%,达到最具竞
争力的存储器编译器。

关键词:SRAM, 存储器编译器, Read Margin, Write Margin

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HIGH PERFORMANCE SRAM DESIGN
METHODOLOGY USING PILER

ABSTRACT

In recent years, many IP vendors have been devoted to the
development of piler. The petitiveness of SRAM
compiler is the area and speed advantage. Facing petitors, this
paper proposes to use the design of two memory architectures in the same
piler for area and speed optimization. The result has achieved a
chip area improvement of 20% smaller and a speed improvement of 15%
faster than parable products in the industry and is considered the
petitive design in piler.

KEY WORDS: SRAM, piler, Read Margin, Write Margin

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目录图片
图 1 SOC 中存储器的使用情况·························································· 1
图 2 piler 设计流程图···················································· 3
图 3 MC2 工具整合界面图································································· 3
图 4 plier 整合流程图···················································· 4
图 5 piler 输入文件···························&