文档介绍：华中科技大学
硕士学位论文
LVDS接收器中时钟数据恢复电路的研究与设计
姓名:王双洋
申请学位级别:硕士
专业:微电子学与固体电子学
指导教师:刘政林
20080520
摘要
低电压差分信号技术(LVDS)以低电压摆幅的高速差动信号传输数据,可以实
现点对点或一点对多点的连接,具有低功耗、低误码率、低串扰和低辐射等特点,
能够在广泛的应用领域里解决高速数据传输的瓶颈问题。LVDS 接收器芯片已成为目
前高速接口芯片市场的研究热点。
本文主要讨论了应用于平板显示器中 LVDS 接收器芯片的研究与设计。芯片采
用“自顶向下”和“由底向上”相结合的正向设计方法。首先按照接收器芯片需完
成的功能,确定系统的结构。数据在传输过程中受抖动和偏移的影响会使数据眼图
的有效采样区间减小,造成采样误差。接收器需要对这些抖动和偏移进行处理,恢
复出正确的采样数据。因此,我们将接收器划分为 Deskew 模块,时钟数据恢复模块
和采样及串并转换电路模块。接着对电路各个模块进行分析设计,最后对芯片进行
全局仿真验证。本文的研究重点是时钟数据恢复电路,详细介绍了此模块中边沿检
测器,相位内插器和采样时钟产生器等子电路的设计过程,并给出相应的仿真结果
和分析。
在前面研究的基础上,采用 TSMC 90 nm Mix-Signal Salicide()和 TSMC
90 nm tcbn90lphp 工艺分别完成了模拟和数字部分的设计,并对接收器芯片全局功能
进行仿真。仿真结果表明,芯片可以支持的单通道最大数据传输率为 Gbps,能够
容忍的抖动和偏移达到±250 ps,同时在低频时产生使能关断信号,使系统功耗降低。
仿真结果表明本设计指标达到既定的要求。

关键词:低压差分信号抖动和偏移时钟数据恢复相位内插器串并转换
I
Abstract
Low-Voltage Differential Signaling (LVDS) transfers data using high speed
differential signal with a low voltage swing, which can achieve a point-to-point or
point-to-multipoint connections. Since it has many advantages such as low power, low
BER, low crosstalk and low radiation, it can be helpful to solve the bottleneck problem of
high speed data transferring in extensive application fields. LVDS receiver has e the
star of the high speed I/O interface chip research.
In this paper, the research and design of a LVDS receiver applied in Flat Panel
Display is demonstrated. We design the chip by means of “top-down” and “bottom-up”
mixed technique. Firstly, according to the functions the IC should have, the structure of
the system is determined. The data eye’s effective sampling margin is degraded by the
effect of jitter and skew during the transmission, which may lead to sampling error. A
receiver is designed to handle this jitter and skew and recover the correct sampled data.
We divide our receiver into Deskew module, Clock and Data Recovery module and
Sampling & Serial to parallel (S2P) module based on the analysis. Secondly, we wo